Scan Design: DFT Implementation for Manufacturing Test
Design for Test (DFT) is the discipline of inserting dedicated test structures into a digital design so that manufacturing defects can be efficiently detected after fabrication. The dominant DFT technique is scan design, in which the flip-flops of a circuit are reconfigured into shift registers (scan chains) during test mode. This allows an external tester to directly control and observe internal state, transforming an otherwise intractable sequential test problem into a manageable combinational one.
This article walks through the full scan flow: scan flip-flops and chains, scan insertion, the standard fault models, ATPG, coverage metrics, on-chip test compression, and at-speed (transition delay) testing. The goal is to give RTL and physical design engineers the practical depth needed to bring up a test-ready netlist.
Quick Summary
| Scan Design | Replace flops with scan cells, stitch into chains for full controllability/observability |
| ATPG | Algorithmically generates patterns to detect modeled faults (stuck-at, transition, path-delay) |
| Compression | EDT/decompressor + MISR reduce pattern volume and pin count by 10-100x |
| At-Speed | LOC/LOS launch test functional-speed paths to catch timing-related defects |
Scan Design Fundamentals
Scan Flip-Flops
The core building block of scan is the scan flip-flop, a standard D flip-flop augmented with a 2-to-1 multiplexer on its data input. A scan enable (SE) signal selects between two modes:
- Functional mode (SE = 0): The flop captures data from the normal functional path (D input)
- Shift mode (SE = 1): The flop captures data from the scan input (SI), connected to the previous cell in the chain
This mux-D scan cell is the most common style. The added mux increases cell area (typically 5-10% area overhead across the design) and adds delay to the functional data path, which the synthesis tool must budget for. Other styles exist, such as clocked-scan and LSSD (Level-Sensitive Scan Design) using master-slave latches with separate test clocks, the latter favored for clock-domain robustness in some methodologies.
Scan Chains
During scan insertion, scan flops are connected output-to-input (SO of one cell drives SI of the next) to form a scan chain, effectively a long shift register. Each chain has a dedicated scan input (SI) pin and scan output (SO) pin at the chip boundary. A design typically contains many parallel chains to keep the longest chain short, since the number of shift cycles per pattern equals the length of the longest chain.
Test operation proceeds in three phases per pattern:
- Shift-in: With SE = 1, the desired test stimulus is shifted into all flops over N clock cycles (N = chain length).
- Capture: With SE = 0, one (or two) functional clock pulse(s) launch the response of the combinational logic into the flops.
- Shift-out: With SE = 1, the captured response is shifted out and compared against expected values, while the next pattern is simultaneously shifted in.
Scan Insertion Flow
Scan insertion (also called scan stitching) is performed on the gate-level netlist, usually inside the synthesis tool after mapping. The major steps are:
- Scan replacement: Map functional flops to their scan-equivalent library cells.
- Scan configuration: Define the number of chains, scan I/O pins, clock and scan-enable signals.
- Scan stitching: Connect cells into chains, respecting clock domains and clock edges (positive- and negative-edge flops are kept in separate segments or ordered to avoid hold violations).
- DRC checks: Run scan design-rule checks to confirm every flop is controllable and observable, clocks are controllable from primary inputs, and asynchronous sets/resets are held inactive during shift.
Scan-ability requires that all clocks and asynchronous control signals be controllable from primary inputs (or test-control logic) during test. Uncontrolled clock gating, internally generated resets, and combinational feedback loops are the most common reasons a flop fails scan DRC and becomes untestable.
Fault Models
ATPG targets fault models, abstractions of physical defects that the tool can reason about. The three workhorse models are stuck-at, transition (at-speed), and path-delay faults.
Stuck-At Faults
The stuck-at fault model assumes a net is permanently tied to logic 0 (stuck-at-0) or logic 1 (stuck-at-1), independent of the driving logic. Each signal line therefore has two potential faults. Detecting a stuck-at fault requires activating it (driving the line to the opposite value) and propagating the effect to an observable point. Stuck-at remains the baseline model for catching gross defects such as shorts to power/ground and broken connections.
Transition (Delay) Faults
The transition delay fault model targets defects that slow a gate or net so a transition arrives too late. Each line has a slow-to-rise and a slow-to-fall fault. Detection requires a two-vector sequence: an initialization vector to set the line, then a launch vector to create the transition, captured at functional speed. This catches resistive opens, process variation, and other timing-related defects that stuck-at testing misses.
Path-Delay Faults
The path-delay fault model evaluates the cumulative delay along a specific critical path rather than a single point defect. It is the most accurate timing model but generates enormous fault counts, so it is applied selectively to a list of timing-critical paths (often extracted from static timing analysis) rather than the whole design.
| Fault Model | Defect Targeted | Vectors Needed | Clocking | Pattern Volume |
|---|---|---|---|---|
| Stuck-At | Shorts, opens, gross defects | Single (1 capture) | Slow / DC | Low |
| Transition | Slow gates/nets, resistive opens | Two (launch + capture) | At-speed | Medium-High |
| Path-Delay | Cumulative delay on critical paths | Two (along defined path) | At-speed | Selective (path list) |
| Bridging / IDDQ | Adjacent-net shorts, leakage | Single (quiescent measure) | Static current | Supplemental |
Automatic Test Pattern Generation (ATPG)
ATPG is the algorithmic process of generating input stimuli that detect the modeled faults. Classic combinational algorithms include the D-algorithm, PODEM, and FAN, which solve the dual problem of fault activation and effect propagation to a scan flop or primary output. Because scan converts sequential logic into combinational cones bounded by scan flops, ATPG only has to solve combinational problems, dramatically improving efficiency and coverage.
A typical ATPG run involves:
- Fault list generation: Enumerate all faults from the model and collapse equivalent faults to reduce count.
- Pattern generation: For each undetected fault, find an input assignment that activates and propagates it.
- Fault simulation: Simulate each generated pattern against the full fault list; a single pattern often detects many faults incidentally, allowing the tool to drop them from the target list.
- Compaction: Merge compatible patterns to minimize the final pattern count and thus tester time.
Faults that ATPG cannot detect are classified as untestable (e.g., redundant logic, tied nets) or ATPG-untestable (detectable in principle but blocked by constraints). Reporting these categories is essential to interpreting coverage correctly.
Fault Coverage and Test Coverage
Two distinct metrics quantify test quality, and confusing them is a frequent source of error.
- Fault Coverage: Detected faults divided by the total number of faults in the design, including those proven untestable.
- Test Coverage: Detected faults divided by the number of testable faults (excluding the untestable ones). Test coverage is the metric most closely tied to manufacturing defect-escape rate (DPM) and is usually the higher of the two.
Coverage Formulas
Fault Coverage = Detected Faults / Total Faults
Test Coverage = Detected Faults / (Total Faults − Untestable Faults)
A production sign-off target is typically >99% stuck-at test coverage and >90% transition test coverage. The remaining gap drives defect-per-million (DPM) escape rate at the tester.
Test Compression
As designs grew into millions of gates, raw scan pattern volume began to dominate tester memory and test time, both of which directly drive test cost. Test compression (embedded compression, branded EDT by Siemens/Mentor, or scan compression in other flows) solves this by decoupling the number of external scan channels from the number of internal scan chains.
Decompressor and Compactor Architecture
Compression inserts two hardware blocks around the scan chains:
- Decompressor: Sits on the input side, expanding a small number of external scan-in channels into many short internal chains. It is commonly built from an LFSR or XOR network (a ring generator in EDT) that spreads compressed stimulus across the internal chains.
- Compactor / MISR: Sits on the output side, compacting the many internal chain outputs back onto a few external scan-out channels. A MISR (Multiple-Input Signature Register) compresses an entire response stream into a final signature, while combinational XOR compactors compact per-cycle.
Because there are far more (and much shorter) internal chains than external channels, the shift cycle count per pattern drops sharply, yielding compression ratios of 10x to over 100x in both pattern volume and test time.
Compression Ratio
Compression Ratio ≈ (Number of Internal Chains) / (Number of External Channels)
Equivalently, it is the ratio of uncompressed to compressed test data volume (or test cycles). Achievable ratios are limited by pattern care-bit density and unknown (X) sources.
Handling Unknown (X) States
Unknown values from uninitialized memories, non-scan flops, or bus contention can corrupt a MISR signature, masking real defects. Compression flows mitigate this with X-masking logic (gating suspect chains before the compactor) and X-bounding (forcing known values at X sources during test). Robust X-handling is essential to preserve observability under high compression.
At-Speed Testing
Stuck-at patterns run at low (DC) frequency and cannot catch timing defects. At-speed testing applies the launch and capture clock edges at functional frequency to exercise transition and path-delay faults. Two clocking schemes dominate, differing in how the transition is launched.
Launch-On-Capture (LOC)
Also called broadside testing. The initialization vector is shifted in, scan enable is de-asserted, and then two rapid functional clock pulses are applied: the first (launch) propagates data through the functional logic to create the transition, and the second (capture) captures the response. LOC does not stress the scan enable timing, so SE can be a slow signal, but it requires ATPG to find a launch vector reachable through the functional logic, which can lower coverage.
Launch-On-Shift (LOS)
Also called skewed-load testing. The transition is launched from the last shift cycle by toggling scan enable, then one capture pulse follows. LOS generally achieves higher coverage and easier pattern generation, but it demands that scan enable switch at functional speed, which complicates timing closure on the high-fanout SE net (often requiring a pipelined or balanced SE distribution).
Both schemes require careful at-speed clock control, frequently using on-chip PLL clocks gated by an OCC (On-Chip Clock Controller) to deliver precisely timed, glitch-free launch/capture pulses while the slow tester handles the shift clock.
Scan Chain Ordering
The logical scan order produced during synthesis is rarely optimal for the physical layout. After placement, the scan chains are reordered so that adjacent cells in a chain are physically close, minimizing scan routing wirelength and congestion. Key considerations during reordering:
- Clock-domain integrity: Cells must stay grouped by clock domain and clock edge; mixing edges within a segment invites shift-mode hold violations.
- Wirelength minimization: A travelling-salesman-style ordering reduces scan net length and routing resources.
- Lock-up latches: Insert level-sensitive lock-up latches at clock-domain or edge boundaries to absorb clock skew between segments during shift.
- Balanced chain lengths: Keep chains close to equal length so no single chain dominates the shift cycle count.
Reordering must preserve the logical chain membership the ATPG tool expects, so the updated order is back-annotated to the test flow to keep patterns valid.
Implementation Best Practices
- Plan DFT early: Define scan architecture, compression ratio, and pin budget during RTL planning, not after place-and-route.
- Make all clocks and resets controllable: Add test-mode bypass for internally generated clocks, gated clocks, and asynchronous resets so every flop is scannable.
- Budget for the scan mux: Account for scan-cell area and the extra data-path delay during synthesis timing closure.
- Balance and shorten chains: Use many balanced chains to cut shift cycles; the longest chain sets test time.
- Insert lock-up latches at domain boundaries: Protect shift operation from inter-chain clock skew.
- Control X sources: Identify uninitialized memories and non-scan logic; apply X-bounding or masking before enabling compression.
- Run at-speed (transition) ATPG: Stuck-at alone is insufficient for modern nodes; add transition and selective path-delay patterns.
- Close timing on scan enable for LOS: If using launch-on-shift, treat SE as a timed signal with balanced distribution.
- Sign off on test coverage, not just fault coverage: Track untestable faults and resolve unexpected coverage gaps before tape-out.
- Validate patterns in simulation: Run zero-delay and timing-aware pattern simulation to confirm tester-correlation before committing to silicon.
Conclusion
Scan design is the foundation of modern manufacturing test. By converting flip-flops into controllable, observable scan cells and stitching them into chains, engineers turn a hopeless sequential test problem into a tractable combinational one that ATPG can solve with high coverage. Layering on test compression tames pattern volume and tester cost, while at-speed transition testing catches the timing defects that stuck-at patterns cannot.
A successful DFT implementation requires early architectural planning, disciplined handling of clocks, resets, and X-sources, and careful sign-off on test coverage and tester correlation. Done well, scan DFT delivers the low defect-per-million escape rates that high-volume production demands.
Vcores provides complete DFT services, from scan insertion, ATPG, and compression architecture to at-speed test bring-up, along with silicon-proven, test-ready IP cores for seamless integration into your ASIC and SoC designs.
