I2S Audio Interface: Digital Audio Design for SoC Engineers
I2S (Inter-IC Sound) is the dominant serial bus for carrying PCM digital audio between ICs: between an SoC and an audio codec, between a DAC and an amplifier, or across an FPGA fabric boundary. Originally defined by Philips in 1986, the I2S standard separates the audio data line from the clock and channel-select lines, which keeps timing margins generous and jitter requirements tractable. This guide gives the technical depth an SoC or FPGA engineer needs to integrate, configure, and verify an I2S link.
Quick Summary
| Signals | SCK (bit clock), WS (word select / LRCLK), SD (serial data); optional MCLK |
| Data format | 2's-complement MSB-first PCM, sampled on the SCK rising edge |
| Channels | Stereo (L/R via WS) natively; multi-channel via TDM framing |
| Typical use | SoC-to-codec audio, DAC/ADC streaming, FPGA audio pipelines |
I2S Signal Description
The classic I2S bus uses three lines for unidirectional audio. A given device is the controller (formerly "master") if it generates SCK and WS; the peripheral ("slave") follows them. Either the transmitter or the receiver may be the controller.
- SCK (Serial / Bit Clock, also BCLK): One pulse per data bit. Frequency = sample rate × bits-per-frame. Data is clocked out on the falling edge and sampled by the receiver on the rising edge, giving half a bit period of setup/hold margin.
- WS (Word Select, also LRCLK / FS): Selects the channel of the current word. WS low = left channel, WS high = right channel. WS runs at exactly the sample rate (Fs) and its transitions delimit the audio frame.
- SD (Serial Data, also SDATA / DIN / DOUT): The PCM payload, MSB first, in 2's-complement form. A separate SD line is used per data direction (one for playback, one for capture).
- MCLK (Master / System Clock): Optional over-sampling clock supplied to the codec's internal sigma-delta converters and digital filters. It is an integer multiple of Fs and is not part of the original I2S spec, but nearly all modern codecs require it.
The Defining Feature: One-Bit Delay
The signature of true I2S is that the MSB of each word is delayed by exactly one SCK period after the WS edge. This delay decouples the data timing from the precise instant of the channel transition, which is what makes the format tolerant of transmitter/receiver word-length mismatches: extra LSBs are simply ignored or zero-padded, and the MSB always lands in a predictable place.
Signal Roles at a Glance
| Signal | Aliases | Driven By | Rate | Function |
|---|---|---|---|---|
| SCK | BCLK, SCLK | Controller | Fs × bits × ch | One pulse per data bit |
| WS | LRCLK, FS | Controller | Fs | Channel select / frame sync |
| SD | SDATA, DIN/DOUT | Transmitter | — | MSB-first 2's-complement PCM |
| MCLK | SYSCLK, MCK | Clock source | N × Fs | Codec over-sampling clock (optional) |
I2S vs Left-Justified vs Right-Justified
The same three wires carry three closely related framings. Codecs are usually configurable for all of them, so matching the controller and peripheral setting is a common bring-up step.
Standard (Philips) I2S
MSB appears one BCLK cycle after the WS transition. Word length is independent of the slot width; if SCK provides more bits than the data resolution, the trailing bits are don't-care. This is the most robust and most widely supported mode.
Left-Justified (MSB-Justified)
MSB appears on the WS transition (no one-bit delay), aligned to the start of the slot. Unused LSBs trail at the end of the slot. Common on older DACs.
Right-Justified (LSB-Justified)
The LSB is aligned to the end of the slot (just before the next WS edge). Because the bit position of the MSB depends on the word length, both ends must agree on the exact resolution (16/24/32-bit), making this the least flexible mode.
Clock Relationships: BCLK, LRCLK, and MCLK
All I2S timing derives from the sample rate Fs. Getting the integer ratios right is the heart of audio clock design.
Core Clock Formulas
Bit clock: BCLK = Fs × bits_per_sample × channels
Word select: LRCLK (WS) = Fs
Master clock: MCLK = N × Fs, where N ∈ {128, 256, 384, 512, 768}
Example (stereo, 48 kHz, 32-bit slots): BCLK = 48000 × 32 × 2 = 3.072 MHz, with MCLK = 256 × 48000 = 12.288 MHz.
Why 256 × Fs?
The 256× (and the 11.2896/12.288 MHz family) values are not arbitrary. They are the lowest common multiples that produce clean integer dividers for both the 44.1 kHz (CD) and 48 kHz (professional/video) clock families from a single crystal. A 24.576 MHz oscillator divides cleanly to the 48 kHz family; 22.5792 MHz serves the 44.1 kHz family. Many systems carry both crystals, or use a fractional-N PLL, precisely because 44.1 and 48 kHz are not integer-related.
BCLK-to-MCLK Synchronicity
BCLK and LRCLK should be generated by dividing MCLK inside the same clock source so that all three remain phase-coherent. If BCLK is derived from an unrelated clock, the codec's internal resampler must absorb the drift, which raises jitter and can produce periodic clicks. For low-jitter audio, the codec PLL or the SoC audio PLL should be the single root.
Sample Rates, Bit Depths, and Clock Budget
The table below lists common stereo configurations with 256× MCLK and 64 BCLK-per-frame (i.e. 32-bit slots). Reduce the slot width to 16 bits and BCLK halves accordingly.
| Sample Rate (Fs) | MCLK (256 × Fs) | BCLK (64 × Fs) | Crystal Family | Typical Use |
|---|---|---|---|---|
| 8 kHz | 2.048 MHz | 0.512 MHz | 48 k | Telephony / voice |
| 44.1 kHz | 11.2896 MHz | 2.8224 MHz | 44.1 k | CD audio |
| 48 kHz | 12.288 MHz | 3.072 MHz | 48 k | Video / pro audio |
| 96 kHz | 24.576 MHz | 6.144 MHz | 48 k | Hi-res audio |
| 192 kHz | 49.152 MHz | 12.288 MHz | 48 k | Studio / mastering |
Bit Depth Choices
- 16-bit: 96 dB theoretical dynamic range; CD and most consumer playback.
- 24-bit: 144 dB range; the practical professional standard, usually carried in 32-bit slots.
- 32-bit: Common slot width even when only 24 valid bits exist; simplifies DMA word alignment.
TDM: Multi-Channel Audio on One Data Line
Standard I2S carries two channels (L/R) per SD line. TDM (Time-Division Multiplexing) extends this by packing many channels into a single frame on one SD line, which is essential for multi-mic arrays, surround systems, and automotive head units.
How TDM Differs from I2S
- Frame sync replaces LRCLK: WS becomes a short FSYNC pulse marking the start of the frame rather than a 50% duty L/R clock.
- N slots per frame: TDM4, TDM8, and TDM16 carry 4, 8, or 16 slots. Each slot is a fixed width (commonly 16 or 32 BCLKs).
- Slot assignment: Each codec on the bus is configured to drive or listen on specific slots, so several devices share one SD line without contention.
TDM Bit-Clock Calculation
BCLK = Fs × slots × slot_width
Example (TDM8, 48 kHz, 32-bit slots): BCLK = 48000 × 8 × 32 = 12.288 MHz on a single SD line carrying 8 channels.
Because BCLK scales with channel count, high slot counts at high sample rates push BCLK into the tens of MHz, where PCB signal integrity and BCLK-to-data skew become the limiting factors.
TDM Mode Comparison
| Mode | Slots | BCLK @ 48 kHz, 32-bit slots | Typical Application |
|---|---|---|---|
| Stereo I2S | 2 | 3.072 MHz | Headphone / line out |
| TDM4 | 4 | 6.144 MHz | 2-way stereo amp + feedback |
| TDM8 | 8 | 12.288 MHz | 7.1 surround, mic arrays |
| TDM16 | 16 | 24.576 MHz | Automotive / pro mixing |
Clock Domain Considerations
In an SoC or FPGA, the audio pipeline almost always crosses between the audio clock domain (BCLK/MCLK) and the system/bus domain (e.g. AXI, AHB at 100–500 MHz). Handling this correctly is the difference between clean audio and intermittent pops.
Asynchronous FIFO Buffering
Use a dual-clock (asynchronous) FIFO with Gray-coded pointers between the I2S serial logic and the DMA/bus interface. The FIFO absorbs the rate difference; its depth must cover the worst-case DMA latency plus bus arbitration jitter. Sizing too shallow causes underrun (playback) or overrun (capture).
Sample-Rate Conversion (SRC / ASRC)
When the audio source and sink run on unrelated clocks (e.g. 44.1 kHz Bluetooth in, 48 kHz codec out), an Asynchronous Sample-Rate Converter resamples in real time, tracking the slowly drifting ratio. This is mandatory whenever two independent crystals feed the same stream.
Jitter and PLL Placement
Audible artifacts correlate with jitter on the clock that actually drives the DAC. Place the cleanest, lowest-jitter clock source at the codec, and avoid regenerating MCLK through long, noisy logic paths. A fractional-N PLL with good phase noise is preferable to bit-banged or heavily divided clocks for the final converter.
Codec Interfacing
A real audio codec needs two logically separate interfaces, and a robust driver brings them up in the right order.
Two Buses, One Device
- Control bus (I2C or SPI): Configures registers—sample rate, format, gain, routing, PLL settings. Low speed, used at init and for volume/mute changes.
- Data bus (I2S/TDM): Streams the actual audio samples continuously once configured.
Bring-Up Sequence
- Apply power rails in the codec's specified order; release reset.
- Start MCLK and wait for the codec PLL to lock.
- Configure registers over I2C/SPI: format (I2S/LJ/RJ), word length, controller/peripheral role, slot map for TDM.
- Enable BCLK and LRCLK, then un-mute the output path last to avoid the startup "pop".
Implementation Best Practices
- Single clock root: Derive MCLK, BCLK, and LRCLK from one PLL/oscillator so all three stay phase-coherent and low-jitter.
- Match the format on both ends: Confirm standard I2S vs left/right-justified and WS polarity before debugging the analog chain.
- Use 32-bit slots for 24-bit data: It simplifies DMA alignment and lets you change resolution without re-timing BCLK.
- Size the async FIFO for worst-case latency: Account for DMA burst gaps and bus arbitration, then add margin to prevent under/overrun.
- Mute around transitions: Mute the path before changing sample rate, format, or routing, and un-mute last during bring-up.
- Mind BCLK/data skew at high rates: For 192 kHz and high TDM counts, keep BCLK and SD trace lengths matched and short, with a solid ground reference.
- Provide both crystal families when needed: Use 22.5792 MHz for 44.1 k and 24.576 MHz for 48 k, or an ASRC, rather than forcing one through a lossy resampler.
- Verify with a known tone: A full-scale sine and an FFT quickly expose format errors, bit-depth truncation, and channel swaps.
Conclusion
I2S remains the workhorse digital audio interface because its three-wire, clock-separated structure keeps timing simple and jitter manageable—while TDM scales the same fabric to many channels. The engineering effort lives in the clocking: getting the MCLK/BCLK/LRCLK ratios, format, and clock-domain crossings right.
For SoC and FPGA designs, treat the audio path as a clocking problem first: choose a clean clock root, buffer the bus-domain crossing with a properly sized async FIFO or ASRC, and bring the codec up in a deterministic, mute-last sequence.
Vcores offers silicon-proven audio interface IP cores—configurable I2S and multi-slot TDM controllers with integrated FIFOs, clock generation, and verification environments—for seamless integration into your FPGA and ASIC audio subsystems.
