Why Low Power Design Matters
Low power design has become a critical concern across all semiconductor applications. From extending battery life in mobile devices to reducing cooling costs in data centers, power optimization is now as important as performance and area in the PPA (Power, Performance, Area) tradeoff.
Power Components in CMOS
Total Power = Dynamic Power + Static Power
- Dynamic Power: Pdyn = α × C × V2 × f
- Static Power: Pstatic = Ileak × V
Where: α = activity factor, C = capacitance, V = voltage, f = frequency, Ileak = leakage current
RTL-Level Power Optimization
1. Clock Gating
The most effective technique for reducing dynamic power:
- Disable clock to idle registers
- Can reduce dynamic power by 20-60%
- Implemented via AND/OR gates or ICG cells
Clock Gating Example
// Without clock gating - always consumes power always_ff @(posedge clk) if (enable) data_reg <= data_in; // With clock gating - saves power when idle assign gated_clk = clk & enable; always_ff @(posedge gated_clk) data_reg <= data_in; // Using ICG (Integrated Clock Gating) cell ICG_CELL icg_inst ( .CLK(clk), .EN(enable), .GCLK(gated_clk) );
2. Operand Isolation
Prevent unnecessary switching in combinational logic:
- Gate inputs to unused functional units
- Use enable signals to isolate operands
- Reduces activity factor α
3. Data Encoding
- Gray Coding: Reduce transitions on counters/addresses
- Bus Inversion: Invert data if >50% bits switching
- One-Hot vs Binary: Choose based on switching patterns
4. Memory Organization
- Use multiple smaller RAMs instead of one large RAM
- Enable only active memory banks
- Choose appropriate memory type (register file vs SRAM)
Architecture-Level Optimization
1. DVFS (Dynamic Voltage and Frequency Scaling)
Adjust voltage and frequency based on workload:
- P ∝ V2 × f means voltage reduction is very effective
- Requires voltage regulators and clock management
- Multiple operating points (OPPs) defined
Typical DVFS Operating Points
| Mode | Voltage | Frequency | Power |
|---|---|---|---|
| Turbo | 1.1V | 2.0 GHz | 100% |
| Normal | 0.9V | 1.5 GHz | 50% |
| Low Power | 0.7V | 800 MHz | 20% |
2. Power Gating
Completely shut off power to idle blocks:
- Header switches: PMOS between VDD and block
- Footer switches: NMOS between block and VSS
- Retention registers: Preserve state during power-off
- Isolation cells: Prevent floating outputs
3. Multiple Voltage Domains
Different blocks operate at different voltages:
- Critical paths at higher voltage for speed
- Non-critical blocks at lower voltage
- Level shifters at domain boundaries
Synthesis-Level Optimization
1. Multi-Vt Synthesis
Use different threshold voltage cells:
- HVT (High-Vt): Low leakage, slower
- SVT (Standard-Vt): Balanced
- LVT (Low-Vt): Fast, higher leakage
Strategy: Use LVT on critical paths, HVT everywhere else.
2. Gate Sizing
- Upsize gates on critical paths
- Downsize gates on non-critical paths
- Smaller gates = less capacitance = less power
3. Logic Restructuring
- Factor common terms to reduce gates
- Use complex gates (AOI, OAI) when appropriate
- Optimize for low-switching paths first
UPF (Unified Power Format)
Industry standard for specifying power intent:
Key UPF Concepts
- Power Domains: Groups of cells with common power
- Power States: ON, OFF, RETENTION
- Isolation: Clamp outputs when domain is off
- Retention: Save/restore state across power cycles
- Level Shifters: Translate between voltage levels
UPF Example
# Create power domain create_power_domain PD_CPU -include_scope # Define power states add_power_state PD_CPU.primary \ -state ON {-supply_expr {power == `{FULL_ON, 0.9}}} \ -state OFF {-supply_expr {power == `{OFF}}} # Add isolation set_isolation iso_cpu \ -domain PD_CPU \ -isolation_power_net VDD_AON \ -clamp_value 0 # Add retention set_retention ret_cpu \ -domain PD_CPU \ -retention_power_net VDD_AON
Low Power Verification
Power-Aware Simulation
- Simulate power state transitions
- Verify isolation cell behavior
- Check retention save/restore
- Validate level shifter insertion
Static Checks
- Missing isolation cells
- Level shifter violations
- Retention register coverage
- Power domain crossing analysis
Conclusion
Low power design requires a holistic approach spanning RTL coding, architecture, synthesis, and physical design. The combination of clock gating, power gating, DVFS, and multi-Vt optimization can reduce power consumption by 50-90% compared to naive implementations.
Vcores designs all IP cores with power optimization in mind, including built-in clock gating, low-power operating modes, and UPF-ready architectures for seamless integration into power-managed SoCs.
