What is RISC-V?
RISC-V (pronounced "risk-five") is an open-standard Instruction Set Architecture (ISA) based on established RISC principles. Unlike proprietary ISAs like ARM and x86, RISC-V is freely available for anyone to implement without licensing fees, making it attractive for custom processor development in academic, commercial, and hobbyist applications.
Why RISC-V Matters
- Open Source: No licensing fees, no royalties
- Modular Design: Base ISA + optional extensions
- Scalable: From microcontrollers to supercomputers
- Clean Slate: Modern design without legacy baggage
- Growing Ecosystem: Tools, software, and IP available
RISC-V ISA Structure
Base Integer ISAs
| ISA | Register Width | Registers | Use Case |
|---|---|---|---|
| RV32I | 32-bit | 32 x 32-bit | Embedded, IoT |
| RV32E | 32-bit | 16 x 32-bit | Ultra-small embedded |
| RV64I | 64-bit | 32 x 64-bit | Application, server |
| RV128I | 128-bit | 32 x 128-bit | Future (draft) |
Standard Extensions
- M: Integer Multiplication and Division
- A: Atomic Instructions (for multicore)
- F: Single-Precision Floating-Point
- D: Double-Precision Floating-Point
- C: Compressed Instructions (16-bit)
- V: Vector Extension (SIMD)
- B: Bit Manipulation
- Zicsr: CSR Instructions
- Zifencei: Instruction-Fetch Fence
Common Combinations
- RV32IMC: Typical embedded microcontroller
- RV32IMFC: With single-precision FPU
- RV64GC: Full general-purpose (G = IMAFD)
- RV64IMAFDC: Linux-capable
RISC-V Instruction Formats
RISC-V uses six basic instruction formats, all 32-bits wide:
R-Type (Register): ADD, SUB, AND, OR, XOR, SLL, SRL, SRA ┌───────┬─────┬─────┬─────┬─────┬─────────┐ │funct7 │ rs2 │ rs1 │func3│ rd │ opcode │ │ 7 │ 5 │ 5 │ 3 │ 5 │ 7 │ └───────┴─────┴─────┴─────┴─────┴─────────┘ I-Type (Immediate): ADDI, LW, JALR ┌────────────┬─────┬─────┬─────┬─────────┐ │ imm[11:0]│ rs1 │func3│ rd │ opcode │ │ 12 │ 5 │ 3 │ 5 │ 7 │ └────────────┴─────┴─────┴─────┴─────────┘ S-Type (Store): SW, SH, SB ┌───────┬─────┬─────┬─────┬─────┬─────────┐ │imm[11:5]│rs2│ rs1 │func3│imm[4:0]│opcode│ │ 7 │ 5 │ 5 │ 3 │ 5 │ 7 │ └───────┴─────┴─────┴─────┴───────┴───────┘ B-Type (Branch): BEQ, BNE, BLT, BGE U-Type (Upper): LUI, AUIPC J-Type (Jump): JAL
RISC-V Pipeline Design
Classic 5-Stage Pipeline
┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐ ┌────────┐
│ IF │→│ ID │→│ EX │→│ MEM │→│ WB │
│ Fetch │ │ Decode │ │Execute │ │Memory │ │WriteBack│
└────────┘ └────────┘ └────────┘ └────────┘ └────────┘
│ │ │ │ │
PC Register ALU Data Register
+4/Branch Read Result Memory Write
Pipeline Hazards
- Data Hazards: RAW dependencies → Forwarding, stalls
- Control Hazards: Branches → Prediction, flush
- Structural Hazards: Resource conflicts → Design around
Advanced Pipeline Features
- Branch prediction (static, dynamic, BTB)
- Superscalar (multiple issue)
- Out-of-order execution
- Speculative execution
Basic RISC-V Core Implementation
Minimal RV32I Datapath
// Simplified RV32I ALU module alu ( input logic [31:0] a, b, input logic [3:0] alu_op, output logic [31:0] result, output logic zero ); always_comb begin case (alu_op) 4'b0000: result = a + b; // ADD 4'b0001: result = a - b; // SUB 4'b0010: result = a & b; // AND 4'b0011: result = a | b; // OR 4'b0100: result = a ^ b; // XOR 4'b0101: result = a << b[4:0]; // SLL 4'b0110: result = a >> b[4:0]; // SRL 4'b0111: result = $signed(a) >>> b[4:0]; // SRA 4'b1000: result = ($signed(a) < $signed(b)) ? 1 : 0; // SLT 4'b1001: result = (a < b) ? 1 : 0; // SLTU default: result = 32'b0; endcase end assign zero = (result == 32'b0); endmodule
Resource Estimates
| Configuration | Logic (LUTs) | Fmax (7-series) |
|---|---|---|
| RV32I (minimal) | ~2,000 | ~100 MHz |
| RV32IMC (typical) | ~5,000 | ~80 MHz |
| RV32IMFC (w/ FPU) | ~15,000 | ~60 MHz |
| RV64GC (Linux) | ~50,000+ | ~50 MHz |
RISC-V Privilege Modes
Privilege Levels
- Machine Mode (M): Highest privilege, always present
- Supervisor Mode (S): For OS kernel
- User Mode (U): For applications
Common Configurations
- M only: Simple embedded systems
- M + U: Protected embedded (RTOS)
- M + S + U: Full OS support (Linux)
Control and Status Registers (CSRs)
- mstatus/sstatus: Status and control
- mie/sie: Interrupt enable
- mip/sip: Interrupt pending
- mtvec/stvec: Trap vector
- mepc/sepc: Exception program counter
- mcause/scause: Trap cause
RISC-V Ecosystem
Open-Source Cores
- PicoRV32: Size-optimized RV32I/M/C
- VexRiscv: Configurable, SpinalHDL
- BOOM: Out-of-order superscalar
- Rocket: In-order, SiFive origin
- CVA6 (Ariane): 64-bit Linux-capable
Toolchain
- GCC: Full RISC-V support
- LLVM/Clang: Full RISC-V support
- Spike: Reference ISA simulator
- QEMU: Full system emulation
Conclusion
RISC-V provides a unique opportunity to build custom processors without licensing constraints. Its modular ISA allows tailoring the processor to specific application needs, from tiny microcontrollers to high-performance application processors.
Vcores provides RISC-V processor cores and integration services, including custom extensions for application-specific acceleration. Our cores are available in various configurations from minimal RV32I to full RV64GC with Linux support.
