SerDes Design: High-Speed Serial Links at 112 Gbps and Beyond
A SerDes (Serializer/Deserializer) is the mixed-signal building block that converts wide parallel buses into a single high-speed differential serial stream and back again. SerDes lanes are the physical-layer workhorses behind PCIe, Ethernet, CXL, USB, and chip-to-chip die interconnects. As per-lane rates pushed past the limits of NRZ signaling, the industry adopted PAM4 to reach 112 Gbps, with 224 Gbps now in development. This guide covers the architecture, modulation trade-offs, equalization, clock recovery, and signal-integrity engineering required to close a modern high-speed link.
Quick Summary
| 112G PAM4 | 56 GBaud, 4 levels, 2 bits/symbol, ~28 GHz Nyquist |
| Equalization | TX FFE + RX CTLE + RX DFE to combat channel loss and ISI |
| Reliability | CDR recovers the clock; RS-FEC pushes BER from 1e-4 to <1e-15 |
SerDes Architecture
A SerDes lane is split into a transmitter (TX) and receiver (RX) that share a common reference clock but recover bit timing independently. The link operates at a serial rate many times higher than the core logic clock, so clock multiplication and gearbox logic sit between the parallel datapath and the analog front end.
TX Serializer
The transmit path narrows a parallel word down to a single serial bitstream:
- Parallel interface: A wide bus (e.g., 32, 64, or 128 bits) from the core clocked at a low frequency
- Encoder: Line coding such as 64b/66b or 128b/130b for DC balance and clock-recovery transition density
- Serializer (MUX tree): A multi-stage multiplexer collapses the parallel word to 1 bit (or 1 PAM4 symbol) per UI
- TX PLL: Multiplies the reference clock up to the serial bit rate that times the output mux
- Output driver: A differential driver (often source-series-terminated, SST) with programmable TX FFE de-emphasis taps
RX Deserializer
The receive path performs the inverse operation but must first recover timing and amplitude from a heavily attenuated, distorted signal:
- Front-end termination & AC coupling: Matches the channel impedance (typically 100 Ω differential) and blocks DC offset
- CTLE: Continuous-time linear equalizer boosts high-frequency content to flatten channel loss
- Sampler/slicer: Quantizes the equalized waveform; PAM4 requires three decision thresholds
- DFE: Decision feedback equalizer cancels post-cursor ISI using prior decisions
- CDR: Clock and data recovery extracts the sampling clock and phase-aligns it to the data eye
- Deserializer & decoder: Reassembles the parallel word and reverses the line code
NRZ vs PAM4 Modulation
Traditional SerDes used NRZ (non-return-to-zero), a 2-level scheme carrying 1 bit per symbol. To double throughput without doubling the symbol rate, PAM4 (4-level pulse amplitude modulation) encodes 2 bits per symbol across four amplitude levels. This lets 112 Gbps run at 56 GBaud instead of the 112 GBaud an NRZ link would require, halving the Nyquist frequency and the associated channel loss.
The benefit is not free. Splitting the same peak-to-peak amplitude into four levels leaves only one-third of the vertical eye opening per level, costing roughly 9.5 dB of SNR. PAM4 also has three eyes that must be aligned, is far more sensitive to noise and reflections, and depends on FEC to reach production bit error rates.
| Parameter | NRZ | PAM4 |
|---|---|---|
| Signal Levels | 2 (binary) | 4 |
| Bits per Symbol | 1 | 2 |
| Baud Rate for 112 Gbps | 112 GBaud | 56 GBaud |
| Nyquist Frequency (112G) | 56 GHz | 28 GHz |
| SNR Penalty | Reference (0 dB) | ~9.5 dB |
| Eye Diagrams | 1 eye | 3 stacked eyes |
| FEC Requirement | Optional | Mandatory (RS-FEC) |
Key SerDes Relationships
Bit Rate: Rb = Baud x log2(M) → PAM4 (M=4): 56 GBaud x 2 = 112 Gbps
Nyquist Frequency: fNyquist = Baud / 2 → 56 GBaud / 2 = 28 GHz
PAM4 SNR Penalty: 20 x log10(3) ≈ 9.5 dB versus NRZ (eye amplitude reduced by factor of 3)
Unit Interval: UI = 1 / Baud → 1 / 56 GBaud ≈ 17.9 ps
Equalization: TX FFE, RX CTLE, and DFE
At 28 GHz Nyquist a typical PCB channel can present 30 dB or more of insertion loss. No sampler can resolve a 4-level eye through that much attenuation, so equalization is distributed across both ends of the link to invert the channel response and reopen the eye.
TX FFE (Feed-Forward Equalizer)
The transmit FFE is a finite-impulse-response filter, usually with a pre-cursor tap, a main cursor, and one or two post-cursor taps. By de-emphasizing low-frequency content and pre-distorting transitions, it pre-compensates for channel loss before the signal is even launched. Because it boosts nothing at the receiver, it adds no noise but is limited by the driver's fixed swing budget.
RX CTLE (Continuous-Time Linear Equalizer)
The CTLE is an analog high-pass/peaking filter at the receiver front end. It applies an adjustable boost near the Nyquist frequency to flatten the overall channel-plus-package response. CTLE is power-efficient and handles both pre- and post-cursor ISI, but as a linear stage it amplifies high-frequency noise and crosstalk along with the signal, so its gain must be traded against the noise floor.
RX DFE (Decision Feedback Equalizer)
The DFE is a non-linear equalizer that subtracts the ISI contribution of previously decided symbols from the current sample. Because it feeds back already-quantized decisions, it cancels post-cursor ISI without amplifying noise, making it ideal for cleaning up residual reflections the CTLE cannot remove. Its drawbacks are timing-critical feedback loops, the risk of error propagation, and an inability to correct pre-cursor ISI. A modern 112G RX typically combines all three: TX FFE pre-shapes, CTLE flattens, and a multi-tap DFE removes what remains.
Clock and Data Recovery (CDR)
The receiver has no separate clock wire, so it must extract the sampling clock from the data transitions themselves. The CDR locks a local clock to the incoming data so each symbol is sampled at the center of its eye, tracking slow drift between the TX and RX reference frequencies (ppm offset) and rejecting jitter.
PLL-Based CDR
A classic PLL-based CDR uses a phase detector, charge pump, loop filter, and voltage-controlled oscillator. The VCO frequency is steered directly to align with the data. It offers excellent jitter filtering and low generated jitter, but a high-frequency VCO at these data rates is area- and power-hungry, and per-lane VCOs are difficult to scale in multi-lane macros.
Phase-Interpolator (PI) CDR
A PI-based CDR keeps a single shared PLL that generates several reference phases, then uses a digitally controlled phase interpolator per lane to pick the optimal sampling phase. This dominates modern multi-lane SerDes because it is compact, fully digital in the loop control, scales easily across many lanes from one PLL, and integrates naturally with adaptive equalization. The trade-off is finite phase-step quantization and a jitter-tracking bandwidth bounded by the interpolator resolution.
Channel Loss and Insertion Loss
The channel is everything between the TX and RX pads: package, vias, PCB traces, connectors, and cables. Its frequency-dependent attenuation is the single biggest constraint on link reach.
- Insertion loss (S21): The dominant impairment, rising with frequency due to dielectric (tanδ) and conductor (skin-effect) losses. A long backplane channel can exceed 30-40 dB at 28 GHz Nyquist.
- Return loss (S11): Reflections from impedance discontinuities at vias, connectors, and stubs that feed energy back into the channel as ISI.
- Insertion loss deviation (ILD): Ripple from resonances and stubs that equalizers struggle to flatten.
- Reach classes: 112G links are categorized as VSR (very short reach, die-to-die), MR (medium reach, chip-to-module), and LR (long reach, backplane), each with a defined loss budget in IEEE 802.3 and OIF-CEI.
Material selection (low-loss laminates such as Megtron 6), back-drilled vias, and short break-out routing are first-order tools for keeping the loss within the equalizer's correction range.
Signal Integrity: ISI, Crosstalk, and Jitter
Closing a 112G eye is fundamentally a signal-integrity problem. The three dominant impairments are intersymbol interference, crosstalk, and jitter.
- ISI (Intersymbol Interference): Channel dispersion smears each symbol's energy into adjacent UIs. ISI is deterministic and is the primary target of equalization (FFE, CTLE, DFE).
- Crosstalk: Coupling from neighboring aggressor lanes. NEXT (near-end) couples at the driver side and FEXT (far-end) at the receiver side; both behave as colored noise that equalizers cannot remove. Tight ground referencing and lane spacing control it.
- Jitter: Timing uncertainty in the sampling instant, decomposed into random jitter (RJ, unbounded, Gaussian) and deterministic jitter (DJ, bounded — including data-dependent, periodic, and duty-cycle distortion components). Total jitter at a target BER sets the horizontal eye closure.
Eye Diagram and BER
The eye diagram overlays many UIs to visualize horizontal (timing) and vertical (voltage) margins. For PAM4 the eye splits into three stacked sub-eyes that must each stay open. Because the raw eyes at 112G are often nearly closed at the slicer input, designers rely on the statistical eye and the bathtub curve, which plot BER versus sampling position to extrapolate margin at target error rates of 1e-12 to 1e-15 without capturing impractically long sample sets.
Forward Error Correction (RS-FEC)
PAM4 links typically deliver a pre-FEC BER around 1e-4 to 1e-6 straight off the slicer — far worse than the 1e-12 to 1e-15 that systems demand. Reed-Solomon FEC (RS-FEC) bridges that gap. The widely deployed RS(544,514) code, known as KP4 FEC, adds 30 symbols of parity per 544-symbol codeword (each symbol is 10 bits), correcting up to 15 symbol errors per codeword. This drives the post-FEC BER below 1e-15 at the cost of a small bandwidth overhead and added latency. KP4 is mandated in the 112G-per-lane Ethernet specifications, which is precisely why PAM4 SerDes are designed to a relatively relaxed pre-FEC error target rather than chasing a wide-open raw eye.
Implementation Best Practices
- Budget the channel first: Establish the insertion-loss profile at Nyquist and confirm it falls within the equalizer's correction range before committing to a reach class.
- Co-design package and PCB: Back-drill via stubs, minimize break-out length, and use low-loss dielectrics to keep S21 ripple and reflections in check.
- Distribute equalization: Combine TX FFE pre-shaping, RX CTLE flattening, and a multi-tap DFE rather than overloading any single stage and its noise budget.
- Enable adaptive training: Use link-training handshakes (e.g., PMD training) so TX FFE taps and RX equalizer settings auto-tune to the actual channel.
- Choose CDR topology for scale: Prefer a shared-PLL phase-interpolator CDR for multi-lane macros; reserve dedicated PLL-per-lane CDR for the lowest-jitter point links.
- Control crosstalk: Maintain continuous ground reference, adequate lane pitch, and shielding to keep NEXT/FEXT below the residual ISI floor.
- Plan for FEC from day one: Architect to a realistic pre-FEC BER target and integrate RS-FEC (KP4) latency and overhead into the system budget.
- Verify with statistical methods: Sign off margins using statistical eye and bathtub-curve analysis tied to the target BER, not just captured time-domain eyes.
Conclusion
Reaching 112 Gbps over real-world channels is a tightly coupled exercise in modulation, equalization, clock recovery, and signal integrity. PAM4 doubles the bits per symbol to keep the Nyquist frequency manageable, but the ~9.5 dB SNR penalty makes a distributed equalization strategy — TX FFE, RX CTLE, and DFE — together with a scalable phase-interpolator CDR and RS-FEC, indispensable for a robust link.
As the industry advances toward 224 Gbps per lane, these same principles intensify: tighter loss budgets, more aggressive equalization, and higher-order modulation push design margins to their limits. Mastering the interaction between channel, equalizer, and clock recovery is the core skill of high-speed SerDes design.
Vcores offers silicon-proven high-speed SerDes IP with configurable PAM4/NRZ modes, adaptive equalization, integrated CDR, and RS-FEC, backed by rigorous signal-integrity verification for your FPGA and ASIC designs.
