USB 3.2: Understanding the Speed Tiers
USB 3.2 represents the latest evolution of the Universal Serial Bus standard, introducing multi-lane operation that doubles the maximum throughput to 20 Gbps. This guide covers the technical details of implementing USB 3.2 in SoC designs, from specification understanding to practical implementation considerations.
USB 3.2 Speed Tiers (Marketing vs Technical Names)
| Technical Name | Marketing Name | Speed | Lanes |
|---|---|---|---|
| USB 3.2 Gen 1x1 | SuperSpeed USB 5Gbps | 5 Gbps | 1 |
| USB 3.2 Gen 1x2 | SuperSpeed USB 10Gbps | 10 Gbps | 2 |
| USB 3.2 Gen 2x1 | SuperSpeed USB 10Gbps | 10 Gbps | 1 |
| USB 3.2 Gen 2x2 | SuperSpeed USB 20Gbps | 20 Gbps | 2 |
USB 3.2 Architecture
Protocol Layer Stack
┌─────────────────────────────────────────┐
│ Application Layer │
├─────────────────────────────────────────┤
│ Function Layer (Class) │
├─────────────────────────────────────────┤
│ USB Device Framework (Chapter 9) │
├─────────────────────────────────────────┤
│ Protocol Layer (PL) │
│ Transaction Packets, Link Management │
├─────────────────────────────────────────┤
│ Link Layer (LL) │
│ Link Training, Power Management │
├─────────────────────────────────────────┤
│ Physical Layer (PHY) │
│ 8b/10b Encoding, SerDes, Equalization │
└─────────────────────────────────────────┘
Key Components
- xHCI Controller: eXtensible Host Controller Interface
- Device Controller: USB device-side protocol handling
- USB 3.2 PHY: Physical layer serializer/deserializer
- Type-C Controller: For Type-C connector support
Multi-Lane Operation (Gen 1x2, Gen 2x2)
How Multi-Lane Works
USB 3.2 Gen 2x2 achieves 20 Gbps by using both TX/RX pairs in a Type-C cable:
- Single-Lane: One TX pair, one RX pair (traditional)
- Dual-Lane: Both TX pairs, both RX pairs simultaneously
- Lane Bonding: Data striped across lanes at packet level
Type-C Connector Pin Usage for USB 3.2 Gen 2x2
Single-Lane Mode: Dual-Lane Mode:
TX1+/TX1- ──► Data TX1+/TX1- ──► Lane 0 TX
RX1+/RX1- ◄── Data TX2+/TX2- ──► Lane 1 TX
TX2+/TX2- ─── Unused RX1+/RX1- ◄── Lane 0 RX
RX2+/RX2- ─── Unused RX2+/RX2- ◄── Lane 1 RX
Requirements for Dual-Lane
- USB Type-C connector (required)
- Cable supporting full Type-C pinout
- Host and device both supporting dual-lane
- Lane negotiation during link training
PHY Integration
PIPE Interface
Standard interface between USB controller and PHY:
- PIPE 4.0: Supports USB 3.0/3.1 Gen 1
- PIPE 5.0: Supports USB 3.1 Gen 2
- PIPE 5.1: Supports USB 3.2 Gen 2x2 (multi-lane)
Key PHY Parameters
| Parameter | Gen 1 (5 Gbps) | Gen 2 (10 Gbps) |
|---|---|---|
| Line Rate | 5 GT/s | 10 GT/s |
| Encoding | 8b/10b | 128b/132b |
| Data Rate | 4 Gbps | 9.7 Gbps |
| TX Swing | 0.4-1.2 Vpp | 0.4-1.2 Vpp |
| Equalization | TX de-emphasis | TX de-emphasis + RX CTLE/DFE |
Link Training and State Machine
LTSSM (Link Training and Status State Machine)
Key states in USB 3.2 link establishment:
- SS.Disabled: SuperSpeed disabled
- Rx.Detect: Detect receiver presence
- Polling: Bit lock, symbol lock, lane polarity
- U0: Active state, normal operation
- U1/U2/U3: Low power states
- Recovery: Re-training after errors
- Loopback: For compliance testing
Gen 2 Specific Training
- Equalization training (TSEQ, TS1, TS2)
- Preset and coefficient negotiation
- LFPS (Low Frequency Periodic Signaling) for handshaking
Power Management
Link Power States
- U0: Active, full power
- U1: Standby, fast resume (~1 μs)
- U2: Standby, slower resume (~1 ms)
- U3: Suspend, deepest sleep
USB Power Delivery (USB PD)
For Type-C implementations:
- Negotiated power up to 240W (USB PD 3.1)
- Separate CC (Configuration Channel) signaling
- PD controller integration
Implementation Challenges
Signal Integrity at 10 GT/s
- Channel loss compensation with equalization
- Careful PCB routing with controlled impedance
- Reference clock jitter management
- SSC (Spread Spectrum Clocking) for EMI
Multi-Lane Synchronization
- Lane-to-lane skew compensation
- Packet striping and reassembly
- Error handling per lane
Backward Compatibility
- Graceful fallback to lower speeds
- USB 2.0 operation in parallel
- Legacy device support
USB 3.2 IP Core Requirements
Host Controller Features
- xHCI 1.2 compliant
- Gen 1x1, Gen 2x1, Gen 2x2 support
- Multiple root hub ports
- DMA engine with scatter-gather
- MSI/MSI-X interrupt support
Device Controller Features
- Configurable endpoints (up to 31)
- All transfer types (Control, Bulk, Interrupt, Isochronous)
- Multiple configurations/interfaces
- LPM (Link Power Management) support
Conclusion
USB 3.2 Gen 2x2 provides the 20 Gbps bandwidth needed for modern high-speed storage, docking stations, and video applications. Implementing USB 3.2 requires careful attention to PHY integration, signal integrity, and link training. The transition to multi-lane operation adds complexity but enables significant throughput improvements.
Vcores offers USB 3.2 controller IP supporting all speed tiers from Gen 1x1 to Gen 2x2, with integrated DMA, comprehensive power management, and PIPE interface for PHY connection. Our IP is silicon-proven and includes full compliance test suites.
